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| INTEGRATED CIRCUITS DATA SHEET UAA3545 Fully integrated DECT transceiver Product specification File under Integrated Circuits, IC17 2001 Sep 06 Philips Semiconductors Product specification Fully integrated DECT transceiver FEATURES * Economical solution for a radio in DECT cordless telephones * Integrated low phase noise VCO with no production tuning required * Fully integrated receiver with high sensitivity * Dedicated DECT PLL synthesizer * 3 dBm output preamplifier with an integrated switch * 3-line serial interface bus * Low current consumption from a 3.2 V supply * Compatible with Philips Semiconductors baseband chips (PCD509xx and PCD80xxx) * Reduced number of control signals. APPLICATIONS * DECT cordless telephones: 1880 to 1930 MHz. GENERAL DESCRIPTION The UAA3545 BiCMOS device is a low power, highly integrated circuit, for Digital Enhanced Cordless Telecommunication (DECT) applications. It features a fully integrated receiver, from antenna filter output to the demodulated data output, a fully integrated VCO, a synthesizer to implement a phase-locked loop for DECT channel frequencies and a TX preamplifier to drive the external transmit power amplifier (CGY20xx series or UAA359x series of Philips integrated circuits). ORDERING INFORMATION TYPE NUMBER UAA3545HL PACKAGE NAME LQFP32 DESCRIPTION plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm UAA3545 The synthesizer's main divider is driven by the prescaler output in the range of 1880 to 1930 MHz and is programmed via a 3-wire serial bus. The reference divider ratio is programmable to 4, 8, 12 or 16. Outputs of the main and reference dividers drive a phase comparator where a charge pump produces phase error current pulses for integration in an external loop filter (only a passive loop filter is necessary). The charge-pump current is set to 4 mA for fast switching. The VCO is powered from an internally regulated voltage source and includes integrated variable capacitance diodes and integrated coils. Its tuning range is guaranteed. The VCO and the synthesizer are switched-on one slot before the active slot to lock the VCO to the required channel frequency. Immediately before the active slot, the synthesizer is switched-off to allow open loop modulation of the VCO during transmission. When opening the loop, frequency pulling (due to switching-off the synthesizer) can be maintained within the DECT specification. The device is designed to operate from a 3.2 V nominal supply. Separate power and ground pins are provided for the different sections of the circuit. Ground leads should be short-circuited externally to prevent large currents flowing across the die and causing damage. All VCC supplies (VCC(REG), VCC(SYN), VCC(RX) and VCC(TX)) must be at the same potential (VCC). VERSION SOT401-1 2001 Sep 06 2 Philips Semiconductors Product specification Fully integrated DECT transceiver UAA3545 QUICK REFERENCE DATA VCC = 3.2 V; Tamb = 25 C; characteristics with a typical value only are not tested; unless otherwise specified. SYMBOL VCC(syn), VCC(reg), VCC(RX), VCC(TX) ICC(SYN) ICC(REG) ICC(RX) ICC(TX) ICC(pd) fo(RF) f(i)XTAL PARAMETER supply voltage CONDITIONS All VCC supplies must be at the same potential (VCC) synthesizer ON VCO ON MIN. 3.0 TYP. 3.2 MAX. 3.6 V UNIT synthesizer supply current VCO, buffer and prescaler regulator supply current receiver supply current transmit preamplifier supply current total supply current in Power-down mode RF output frequency crystal reference input frequency - - - - - 1880 - 5 14 36 12 10 - 7 17 44 15 100 1930 mA mA mA mA A MHz MHz 3.456, - 6.912, 10.368 or 13.824 864 - - +60 fPC Tamb phase comparator frequency ambient temperature - -10 kHz C 2001 Sep 06 3 Philips Semiconductors Product specification Fully integrated DECT transceiver BLOCK DIAGRAM UAA3545 handbook, full pagewidth VCC(RX) VCC(TX) 22 RSSI 12 RXGND 13 TXGND 19 16 RFA RFB 15 14 LNA x SLIC = 1 LIMITER DEMODULATOR 0 1 k SLIC = 1 7 0 SLIC = 1 0 RDATAP 9 11 DATAM SLCCTR UAA3545 SLICER (1) TXA TXB VCO_ON R_ON 20 21 1 AMP PRESCALER 26 10 VREGI SYNGND VREGO REGGND VCOGND 17 CONTROL LOGIC SYNTHESIZER VCO REGULATOR 31 30 27 8 S_CLK 6 4 28 29 18 23 24 5 XTAL 3 VCC(SYN) 32 25 2 MGW108 S_DATA TEST2 DIVGND VMOD VCC(REG) S_EN TEST1 TEST3 VREGDIV CP/VCO tune (1) SLCCTR `switches' shown in position SLCCTR = LOW. Fig.1 Block diagram. 2001 Sep 06 4 Philips Semiconductors Product specification Fully integrated DECT transceiver PINNING SYMBOL VCO_ON VCC(REG) VCC(SYN) S_DATA XTAL S_EN RDATAP S_CLK DATAM SYNGND SLCCTR RSSI RXGND RFB RFA VCC(RX) R_ON TEST3 TXGND TXA TXB VCC(TX) DIVGND VREGDIV VMOD VREGI VCOGND TEST1 TEST2 REGGND VREGO CP/VCOtune Notes PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VCO section power-on control; note 1 regulator positive supply voltage synthesizer positive supply voltage 3-wire bus data signal input reference frequency input; note 2 3-wire bus enable signal input demodulator output voltage 3-wire bus clock signal input switched demodulator output voltage synthesizer ground DATAM switch control signal (see Fig.1) received signal strength intensity voltage output receiver ground received signal input B received signal input A receiver positive supply voltage receiver power-on control; note 3 TEST input 3 (must be connected to GND) transmitter ground transmit amplifier output A transmit amplifier output B transmitter positive supply voltage divider ground divider regulated supply voltage VCO analog modulation voltage input VCO regulated voltage input VCO ground TEST input 1 (must not be connected) TEST input 2 (must not be connected) regulator ground VCO section regulated voltage output charge-pump output/VCO tuning input DESCRIPTION UAA3545 1. Corresponds to the S_PWR of the baseband chip (see Section "Operating modes" for more details). 2. Corresponds to the REF_CLK of the baseband chip. 3. See Section "Operating modes" for more details. 2001 Sep 06 5 Philips Semiconductors Product specification Fully integrated DECT transceiver UAA3545 handbook, full pagewidth 32 CP/VCO tune 30 REGGND 27 VCOGND 31 VREGO 29 TEST2 28 TEST1 26 VREGI 25 VMOD VCO_ON VCC(REG) VCC(SYN) S_DATA XTAL S_EN RDATAP S_CLK 1 2 3 4 24 VREGDIV 23 DIVGND 22 VCC(TX) 21 TXB UAA3545HL 5 6 7 8 20 TXA 19 TXGND 18 TEST3 17 R_ON SYNGND 10 SLCCTR 11 RSSI 12 RXGND 13 RFB 14 RFA 15 VCC(RX) 16 DATAM 9 FCA242 Fig.2 Pin configuration. 2001 Sep 06 6 Philips Semiconductors Product specification Fully integrated DECT transceiver FUNCTIONAL DESCRIPTION Transmit chain VCO AND PRESCALER The fully integrated VCO operates at a multiple of the DECT frequency. It is supplied by an on-chip voltage regulator to minimize frequency disturbances due to supply voltage variations. The VCO signal is fed into a prescaler. A large difference between transmitted and VCO frequencies reduces transmitter-oscillator coupling problems. The output of the prescaler drives the synthesizer main divider. The divider output can also be switched to either the TX preamplifier or the RX LO output buffer. The high isolation obtained from the prescaler ensures very small frequency changes when turning-on the TX preamplifier or the RX section. In TX mode, the oscillator can be modulated directly with GFSK-filtered data at pin VMOD. TX PREAMPLIFIER The TX preamplifier amplifies the RF signal to a level of 3 dBm (typical) which is suitable for use with Philips Semiconductors DECT power amplifiers. Synthesizer MAIN DIVIDER The main divider is clocked by the RF signal from the prescaler at frequencies from 1880 to 1930 MHz. Any main divider ratio from 2176 to 2303 inclusive can be programmed. REFERENCE DIVIDER The reference divider is clocked by the signal at pin XTAL. The circuit operates with levels from 1.2 to 1.8 V (p-p) at a frequency of 3.456 MHz. By programming the `REFD' bits of the serial input register (see Table 1) the reference frequency can be set for 6.912, 10.368 or 13.864 MHz. PHASE COMPARATOR UAA3545 The phase comparator is driven by the output of the main and reference dividers. It produces current pulses at pin CP/VCOtune, the pulse duration being the difference in arrival time of current pulse edges from the two dividers. If the main divider edge arrives first, pin CP sinks current. If the reference divider edge arrives first, pin CP sources current. The DC value of the charge-pump current is defined by an internal resistor. Additional circuitry is included to ensure the gain of the phase detector remains linear even for small phase errors. Serial programming bus A simple 3-line unidirectional serial bus is used to program the circuit. The three lines are data (S_DATA), serial clock (S_CLK) and serial bus enable (S_EN). Data sent to the device are loaded in bursts framed by S_EN. Programming clock edges and their appropriate data bits are ignored until S_EN goes active (LOW). The programmed information is read directly by the main divider when S_EN returns to HIGH. S_DATA and S_EN change value on the falling edge of S_CLK. During synthesizer operation, S_EN should be held HIGH. Only the last 24 bits clocked into the device are retained within the serial register. Additional leading bits are ignored and no check is made on the number of clock pulses. The data format is shown in Table 1. The first bit entered is b23, the last bit is b0. For the main divider ratio, the first bit (b5) is the Most Significant Bit (MSB). The serial bus enable (S_EN) must be LOW to capture new programming data and must be HIGH to switch on the synthesizer. 2001 Sep 06 7 Philips Semiconductors Product specification Fully integrated DECT transceiver Receiver The receiver is a fully integrated RF + IF strip and demodulator for DECT. It provides all the required channel filtering over the DECT band and generates analog RSSI and a switched output for Philips Semiconductors baseband chip. Very few off-chip components are required and all of these can be placed without trimming. The chip is designed to operate with a power supply voltage that can fall to 3.0 V. The input is the RF antenna signal derived from the band filter or the antenna switch. The outputs are the RSSI voltage, representing the instantaneous signal strength and two HIGH-level demodulator output signals RDATAP and DATAM, the latter being switched by SLCCTR to generate the external slicer threshold. During the blind slot, while the PLL is settling, an internal voltage source is activated to precharge the external capacitor (connected to pin DATAM) to a voltage close to the required slicer threshold. Operating modes The operating modes available are: * Normal mode (see Fig.3) * Reduced signal mode (see Fig.4) * Advanced signal mode (see Fig.5). Selection of an operating mode is achieved via the serial interface register (see Table 3). NORMAL MODE (MODE 1) In the normal mode, the synthesizer is ON when S_EN = HIGH and VCO_ON = HIGH, and OFF when S_EN = LOW. When turned ON, the dividers and phase detector are synchronized to avoid a random initial phase error. When turned OFF, the phase detector is synchronized with the dividers to avoid interrupting a charge-pump pulse. This feature requires a signal to be present for a few microseconds on the XTAL pin after S_EN goes LOW. The VCO is ON when the input signal VCO_ON is HIGH. The polarity of VCO_ON is chosen for compatibility with output S_PWR of the baseband chip. When the VCO is turned ON, it takes 50 s (typical) to reach its steady state. The TX preamplifier is ON when bit `TRX' is programmed to `0' and VCO_ON is HIGH. When the TX preamplifier is turned ON, it takes typically 10 s to be ready. The receiver is turned ON when R_ON = HIGH and VCO_ON = HIGH. REDUCED SIGNAL MODE (MODE 2) UAA3545 In the reduced signal mode, the parallel control signals are replaced by serial bus programming. To select this mode, the bit `NEW' of the internal register must be set to `1' and the bit `SPWR' must be reset to `0', timing is then controlled by the S_EN signal. After the register programming, the S_EN rising edge programs the PLL, closes the loop, powers-on the VCO and, if the `TRX' bit = 0, turns ON the TX preamplifier. On the falling edge of the first S_EN pulse, the loop is opened (unless the bit `PLL' is set to 1) and the receiver switches ON if the `TRX' bit = 1. A second pulse on S_EN is required at the end of the wanted slot to power-down the application. The R_ON pin becomes an output in this mode, drives the RX PIN diode and corresponds to the internal power-on signal of the receiver. ADVANCED SIGNAL MODE (MODE 3) In the advanced signal mode, the parallel control signals are partly replaced by serial bus programming. To select this mode, the bit `NEW' and the bit `SPWR' of the internal register must be set to `1'. The S_EN signal will then control the UAA3545 timing (except for timing of a general power-down as this is controlled by the VCO_ON input). The VCO_ON signal should rise at the beginning of the previous slot. After the serial bus has been programmed, the S_EN rising edge programs the PLL, closes the loop and, if the `TRX' bit = 0, turns ON the TX preamplifier. On the falling edge of the first S_EN pulse, the loop is opened (unless the `PLL' bit is set to 1) and the RX section switches ON if bit `TRX' = 1. At the end of the wanted slot, the VCO_ON goes LOW to power-down the whole IC. In fact, the second pulse of the S_EN signal in mode 2 is now replaced by the signal VCO_ON. The R_ON pin becomes an output in this mode, drives the RX PIN diode and corresponds to the internal power-on signal of the receiver. 2001 Sep 06 8 Philips Semiconductors Product specification Fully integrated DECT transceiver Programming Table 1 Serial interface register REGISTER BIT ALLOCATION first in b23 to b20 TEST(2) Notes b19 SLIC(3) b18, b17 REFD(4) b16 to b10 TEST(2) b9 SPWR(5) b8 PLL(6) b7 NEW(5) b6 TRX UAA3545 last in b5 to b0(1) MAIN DIVIDER(7) 1. Bit b5 is the MSB of the main divider coefficient; this comprises bits b5, b4, b3, b2, b1, b0 and b6 (TRX). 2. Test bits b23, b22, b21, b20, b16, b15, b14, b13, b12, b11, b10 must always be programmed to 0. 3. Bit `SLIC' = 1 forces the internal slicer on. In this mode, pin DATAM is connected to an external capacitor. Together with an internal 1 k resistor, it defines the low pass time constant for the slicer threshold voltage. When the bit `SLIC' = 0, the pin RDATAP is connected directly to the demodulator output and delivers an analog signal. Pin DATAM also reflects the demodulator voltage without the internal 1 k resistor when the SLCCTR pin is HIGH. 4. REFD sets the reference divider ratio to 4, 8, 12 or 16 (corresponding respectively to a reference input frequency of 3.456, 6.912, 10.368 or 13.824 MHz) (see Table 4). 5. Bits `NEW', and `SPWR' select the operating mode (see Table 3). 6. Bit `PLL' = 1 forces the PLL to remain on when the VCO is on. 7. The main divider ratio is equal to 2176 + the programmed value (see Table 2). Table 2 Main divider programming BIT b5 0 0 Table 3 b4 0 1 b3 0 0 b2 0 1 b1 0 1 b0 0 1 b6 (TRX) 0 1 MAIN DIVIDER RATIO 2176 + n 2176 2223 SYNTHESIZED FREQUENCY (MHz) 0.864 x (2176 + n) 1880.064 1920.672 Binary equivalent of n Operating mode selection BIT OPERATING MODE b9 (SPWR) 0 0 1 1 Table 4 b7 (NEW) 0 1 0 1 normal mode (mode 1) reduced signal mode (mode 2) do not use advanced signal mode (mode 3) Reference divider ratio programming BIT REFERENCE DIVIDER RATIO REFERENCE INPUT FREQUENCY 3.456 MHz 13.824 MHz 6.912 MHz 10.368 MHz 9 b18 0 0 1 1 2001 Sep 06 b17 0 1 0 1 4 16 8 12 Philips Semiconductors Product specification Fully integrated DECT transceiver LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VCC(syn), VCC(reg), VCC(RX), VCC(TX) Vn Pi(RFA)(max), Pi(RFB)(max) GND Ptot Tstg Tamb Tj Note PARAMETER supply voltage CONDITIONS All VCC supplies must be at the same potential (VCC) MIN. -0.3 UAA3545 MAX. +3.6 V UNIT voltage on any pin maximum input power at pins RFA and RFB difference in ground supply voltage applied between all ground pins total power dissipation storage temperature ambient temperature junction temperature note 1 -0.3 - - - -55 -10 - VCC 15 0.01 300 +125 +60 150 V dBm V mW C C C 1. Ground pins must be short-circuited externally (this is in addition to being short-circuited internally. HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. All pins are compatible with "EIA/JESD22-A114-A Class1 (October 1997)". LATCH-UP Pins S_DATA, TXA and TXB are susceptible to latch-up if a negative current greater than 20 mA is drawn from the respective pin (occurs when the pin voltage is negative with respect to GND). To avoid latch-up, pins TXA and TXB pins must be connected to VCC through coils, and the S_DATA control signal input from the baseband IC must be kept positive with respect to GND. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 100 UNIT K/W 2001 Sep 06 10 Philips Semiconductors Product specification Fully integrated DECT transceiver UAA3545 CHARACTERISTICS VCC = 3.2 V; Tamb = 25 C; fdev = 288 kHz; f(i)XTAL = 13.824 MHz; characteristics with a typical value only are not tested; unless otherwise specified. SYMBOL Supplies VCC(syn), VCC(reg), VCC(RX), VCC(TX) ICC(SYN) ICC(REG) supply voltage All VCC supplies must be at the same potential (VCC) 3.0 3.2 3.6 V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT synthesizer supply current VCO, buffer and prescaler regulator supply current receiver supply current transmit preamplifier supply current total supply current in Power-down mode S_EN = HIGH VCO ON - - 5 14 7 17 mA mA ICC(RX) ICC(TX) ICC(pd) Synthesizer MAIN DIVIDER fo(RF) Rm f(i)XTAL RX mode TX mode - - - 36 12 10 44 15 100 mA mA A RF output frequency main divider ratio 1880 2176 - - - 3.456, 6.912, 10.368 or 13.824 - 1930 2234 - MHz REFERENCE DIVIDER crystal reference input frequency programmed values; see Table 4 MHz V(i)XTAL(p-p) crystal reference input voltage (peak-to-peak value) reference divider ratio input resistance (real part of the parallel input impedance) input capacitance (imaginary part of the parallel input impedance) square wave input; all f(i)XTAL values programmed values; see Table 4 f(i)XTAL = 3.456 MHz 1.2 1.8 V RRD Ri(XTAL) - - 4, 8, 12 or 16 17 - - k Ci(XTAL) f(i)XTAL = 3.456 MHz - 1.5 - pF PHASE COMPARATOR fPC phase comparator frequency - 864 - kHz 2001 Sep 06 11 Philips Semiconductors Product specification Fully integrated DECT transceiver UAA3545 SYMBOL PARAMETER CONDITIONS VCP = 12VCC - MIN. TYP. - MAX. UNIT CHARGE-PUMP OUTPUT Io(CP) VCO fVCO oscillator frequency defined at transmit output, Tamb = -10 to +60 C; note 1 1880 0.3 - - 1930 MHz charge-pump output current 3.5 mA VCP/VCOtune charge pump input voltage and VCO tuning output voltage GVCO GMOD VCO tuning input gain (mean value) VCO modulation input gain defined at transmit output; note 2 defined at transmit output; note 3 VCC - 0.3 V - - 70 2.4 - - MHz/V MHz/V Transmit preamplifier Po(TXA), Po(TXB) Ro(TXA), Ro(TXB) transmit output power transmit output resistance (real part of the parallel output impedance) transmit output capacitance (imaginary part of the parallel output impedance) Tamb = -10 to +60 C; fVCO = 1880 to 1930 MHz; note 1 0 3 200 - - dBm balanced; expressed at high signal - level Co(TXA), Co(TXB) balanced; expressed at high signal - level 0.3 - pF fVCO(feedthru) VCO frequency feedthrough at transmit output CNR25 CNR4686 fo(push) carrier-to-noise ratio at transmit output carrier-to-noise ratio at transmit output frequency shift due to supply voltage drop referred to Po(TXA), Po(TXB); fVCO = 1900 MHz; note 1 carrier offset in closed loop; f = 25 kHz carrier offset; f = 4686 kHz measured dynamically; VCC drop = 100 mV; VCP/VCOtune = 1.2 V; VMOD = 0; TX load = 50 ; note 1 - -20 -15 dBc - - - -65 -135 +10 -56 -129 20 dBc/Hz dBc/Hz kHz fo(pull) frequency shift due to frequency pulling measured 20 s disabling the synthesizer after synthesizer disabled; VCP/VCOtune set by the PLL on fVCO = 1880.064 MHz; VMOD = 0; TX load = 50 ; note 1 transmit output frequency drift during a slot notes 1 and 4 - +5 10 kHz fo(drift) - -6 12 kHz 2001 Sep 06 12 Philips Semiconductors Product specification Fully integrated DECT transceiver UAA3545 SYMBOL Receiver section VRSSI(max) VRSSI PARAMETER CONDITIONS - MIN. TYP. - MAX. UNIT maximum RSSI output voltage RSSI output voltage under high RX input signal level monotonicity over range -96 to -36 dBm Pi(RFA/B) = -33 dBm Pi(RFA/B) = -36 dBm Pi(RFA/B) = -96 dBm 1.9 V - - - - 1.7 1.64 0.3 25 2.0 - - 40 V V V s ton wake-up time from the power-on signal to correct RSSI output input sensitivity intermodulation rejection co-channel rejection adjacent channel rejection bi-adjacent channel rejection rejection with 3 channels separation BER 10-3; note 1 BER 10-5; 10-3; note 1 wanted signal at BER < -83 dBm; level of interference in channels n + 2 and n + 4; note 1 BER < 10-3; wanted channel at -76 dBm; note 1 sB IM - - 33 -96 -92 42 -93 -76 - dBm dBm dBc Rco Ri(n-1) -10 -7.5 20 - - dBc dBc BER < 10-3; wanted channel at 14 -76 dBm; adjacent level referred to wanted channel level; note 1 BER < 10-3; wanted channel at 35 -76 dBm; bi-adjacent level referred to wanted channel level; note 1 BER < 10-3; wanted channel at -76 dBm; n 3 adjacent level referred to wanted channel level; note 1 BER < 10-3; wanted signal at -83 dBm at channel 5: f - fc > 6 MHz; note 2 38 40 Ri(n-2) 42 - dBc Ri(n-3) 45 - dBc RBl rejection of a blocking signal 55 58 - - dBc dBc (fRFmax + 5 MHz) < f < 2 GHz; 48 1780 MHz < f < (fRFmin - 5 MHz) ; note 1 2 GHz < f < 4.32 GHz; notes 1 and 5 Ro(RF) RF input resistance (real balanced; at 1890 MHz part of the parallel input impedance) RF input capacitance (imaginary part of the parallel input impedance) balanced; at 1890 MHz 38 - 60 100 - - dBc Co(RF) - 0.8 - pF 2001 Sep 06 13 Philips Semiconductors Product specification Fully integrated DECT transceiver UAA3545 SYMBOL fi(RF)(max) fi(RF)(min) RLRF GDEM VDEM PARAMETER maximum RF input frequency minimum RF input frequency return loss on matched RF input demodulator gain DC level at demodulator outputs RDATAP and DATAM CONDITIONS - MIN. - - TYP. MAX. 1930 - - - - UNIT MHz MHz dB V/MHz V 1880 balanced; note 1 mean value of fdev = 288 kHz fLO = fRF + 864 kHz 11 - - 15 1.6 1.3 Interface logic input and output pins S_DATA, S_CLK, S_EN, R_ON, VCO_ON, SLCCTR and RDATAP VIH VIL Ibias HIGH-level input voltage note 6 LOW-level input voltage) input bias current HIGH or LOW input levels bit `SLIC' = 1; IOH = 500 A bit `SLIC' = 1; IOL = -500 A mode 2 or 3; VRON = HIGH level; VCC - VRON = 0.5 V mode 2 or 3; VRON = LOW level 1.4 -0.3 -5 - - - VCC +0.4 +5 - 0.4 - - - - V V A V V mA k MHz s VOH(RDATAP) HIGH-level output voltage (pin RDATAP) VOL(RDATAP) IO(RON) ZO(RON) fSCLK(max) tSEN(min) Notes LOW-level output voltage (pin RDATAP) output drive current (pin R_ON) output impedance (pin R_ON) maximum frequency (pin S_CLK) minimum pulse duration (pin S_EN) VCC - 0.4 VCC - 2.5 - - - 0 5 6 10 1 1. Measured and guaranteed only on the Philips evaluation board, including Printed-Circuit Board (PCB) and balun filter with internal slicer. 2. Mean of the values of transmit frequency at VCP/VCOtune = 0.3 and 2.7 V. 3. Measured with VCP/VCOtune = 1.5 V, mean of the values of transmit frequency at VMOD = 0 and 0.5 V. 4. Frequency difference measured during 420 s with VMOD = 0 (no modulation applied), at least 20 s after disabling the synthesizer. 5. Except for three occurrences, as defined in the DECT specification. 6. VIH should never exceed 3.6 V. 2001 Sep 06 14 Philips Semiconductors Product specification Fully integrated DECT transceiver MODE 1 TIMING UAA3545 handbook, full pagewidth RECEIVE MODE S_DATA S_CLK S_EN EXTERNAL VCO_ON EXTERNAL R_ON EXTERNAL XTAL TRANSMIT MODE S_DATA S_CLK S_EN EXTERNAL VCO_ON EXTERNAL R_ON EXTERNAL XTAL TRANSMIT PREAMPLIFIER STATUS SIGNAL ON OUTPUTS TXA, TXB FCA243 Fig.3 Normal mode timing diagram. 2001 Sep 06 15 Philips Semiconductors Product specification Fully integrated DECT transceiver MODE 2 TIMING UAA3545 handbook, full pagewidth RECEIVE MODE S_DATA S_CLK S_EN INTERNAL VCO_ON R_ON OUTPUT EXTERNAL XTAL TRANSMIT MODE S_DATA S_CLK S_EN INTERNAL VCO_ON EXTERNAL XTAL SIGNAL ON OUTPUTS TXA, TXB FCA244 Fig.4 Reduced signal mode timing diagram. 2001 Sep 06 16 Philips Semiconductors Product specification Fully integrated DECT transceiver MODE 3 TIMING UAA3545 handbook, full pagewidth RECEIVE MODE S_DATA S_CLK S_EN EXTERNAL VCO_ON R_ON OUTPUT EXTERNAL XTAL TRANSMIT MODE S_DATA S_CLK S_EN EXTERNAL VCO_ON EXTERNAL XTAL SIGNAL ON OUTPUTS TXA, TXB FCA245 Fig.5 Advanced signal mode timing diagram. 2001 Sep 06 17 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... k, full pagewidth C18 TEST2 TEST1 2001 Sep 06 VCC XTAL APPLICATION INFORMATION Philips Semiconductors Fully integrated DECT transceiver T_GFSK C13 560 pF NPO R11 C66 100 nF C65 6.8 pF C67 6.8 pF VCC 24 23 22 21 TXB TXA C32 8.2 pF L7 12 nH C33 0.82 pF C28 8.2 pF C62 1.8 pF C68 8.2 pF C70 8.2 pF L6 2.7 nH (2) L5 2.7 nH C23 100 nF C69 8.2 pF 8.2 nF 2.2 k NPO 32 VCO_ON C57 100 nF C22 82 pF 1 2 C58 10 F 3 4 31 30 29 28 27 26 25 C31 1 nF S_DATA(1) UAA3545 5 20 19 18 17 9 C40 4.7 nF 10 11 12 13 14 15 16 6 7 8 S_EN R_DATAP L4 12 nH C27 0.82 pF 18 S_CLK TX output VCC C46 8.2 pF ADDITIONAL IMPLEMENTATION T_PWR C42 1.5 pF C 8.2 pF R 470 C 8.2pF RFB RFA L8 6.8 nH SLCCTR RSSI C44 27 pF L9 6.8 nH C40 8.2 pF C43 1.5 pF C41 8.2 pF L10 6.8 nH PA R 470 RF input FCA246 Product specification UAA3545 (1) S_DATA input (pin 4) is subject to latch-up if a negative voltage is applied. The application circuit should be designed to prevent this occurring. (2) TXA and TXB outputs (pins 20 and 21) are subject to latch-up if a negative output voltage occurs. To prevent this happening, the application circuit should use a DC biasing arrangement with L5 and L6 connected to VCC as shown. Fig.6 Evaluation board schematic (mode 3 operation). Philips Semiconductors Product specification Fully integrated DECT transceiver Internal pin configuration PIN 1 4 6 8 11 7 9 SYMBOL VCO_ON S_DATA S_EN S_CLK SLCCTR RDATAP DATAM 7, 9 MGW234 UAA3545 INTERNAL CIRCUIT 1, 4, 6, 8, 11 MGW235 12 RSSI 12 MGW237 14 15 RFB RFA 14 15 MGW238 17 R_ON 17 MGW239 2001 Sep 06 19 Philips Semiconductors Product specification Fully integrated DECT transceiver UAA3545 PIN 20 21 SYMBOL TXA TXB INTERNAL CIRCUIT 20 21 MGW240 25 VMOD 25 MGW241 31 VREGO 31 MGW242 32 CP/VCOtune 32 MGW243 2001 Sep 06 20 Philips Semiconductors Product specification Fully integrated DECT transceiver RECEIVED SIGNAL STRENGTH INTENSITY UAA3545 handbook, full pagewidth 2 MGW233 VRSSI (V) 1.6 1.2 0.8 0.4 0 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Pi(RFA/B) (dBm) 0 Fig.7 RSSI output as a function of input power at pins RFA and RFB. 2001 Sep 06 21 Philips Semiconductors Product specification Fully integrated DECT transceiver PACKAGE OUTLINE LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm UAA3545 SOT401-1 c y X 24 25 17 16 ZE A e E HE wM bp 32 1 8 9 L detail X Lp A A2 A1 pin 1 index (A 3) e bp D HD ZD wM B vM A vM B 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.15 0.05 A2 1.5 1.3 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 5.1 4.9 E (1) 5.1 4.9 e 0.5 HD 7.15 6.85 HE 7.15 6.85 L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT401-1 REFERENCES IEC 136E01 JEDEC MS-026 EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-27 00-01-19 2001 Sep 06 22 Philips Semiconductors Product specification Fully integrated DECT transceiver SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. UAA3545 If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2001 Sep 06 23 Philips Semiconductors Product specification Fully integrated DECT transceiver Suitability of surface mount IC packages for wave and reflow soldering methods UAA3545 SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable 2001 Sep 06 24 Philips Semiconductors Product specification Fully integrated DECT transceiver DATA SHEET STATUS DATA SHEET STATUS(1) Objective specification PRODUCT STATUS(2) Development DEFINITIONS UAA3545 This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Preliminary specification Qualification Product specification Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2001 Sep 06 25 Philips Semiconductors Product specification Fully integrated DECT transceiver NOTES UAA3545 2001 Sep 06 26 Philips Semiconductors Product specification Fully integrated DECT transceiver NOTES UAA3545 2001 Sep 06 27 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2001 SCA73 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 403506/01/pp28 Date of release: 2001 Sep 06 Document order number: 9397 750 08151 |
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